The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for capacitor plates is conductively doped polysilicon. Such is utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying topography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors used for the deposition.
The prior art has recognized that capacitance of a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. Such roughness is typically transferred to the cell dielectric and overlying polysilicon layer interfaces, resulting in a larger surface area for the same planar area which is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper polysilicon surface. Such include low pressure chemical vapor deposition (LPCVD) techniques. Yet, such techniques are inherently unpredictable or inconsistent in the production of a rugged polysilicon film.
One type of polysilicon film which maximizes a roughened outer surface area is hemispherical grain (HSG) polysilicon typically provided to a thickness of from 300 Angstroms to 400 Angstroms. Such can be deposited or grown by a number of techniques. One technique includes direct LPCVD formation at 590.degree. C. Another includes formation by first depositing an amorphous silicon film at 550.degree. C. using He diluted SiH.sub.4 (20%) gas at 1.0 Torr, followed by a subsequent high temperature transformation anneal. Regardless, existing techniques subject the substrate to an HF dip prior to HSG formation. The HF dip was conducted to leave bonded hydrogen atoms at the outer surface of the underlying layer. This outer exposed hydrogen was believed to function as a necessary seed layer for formation of the HSG poly during subsequent deposition.
Needs remain for providing improved methods of depositing rough HSG polysilicon on a substrate in semiconductor processing.